The present invention relates generally to an integrated circuit (IC) design, and more particularly to a tie-off circuit capable of protecting a circuit element during an electrostatic discharge (ESD) event.
A gate oxide of a metal-oxide-semiconductor (MOS) transistor of an IC is most susceptible to damage. The gate oxide may be destroyed by being contacted with a voltage only a few volts higher than a supply voltage. It is understood that a regular supply voltage in an IC is 5.0, 3.3 volts or even lower. Electrostatic voltages from common environmental sources can easily reach thousands, or even tens of thousands of volts. Such voltages are destructive even though the charge and any resulting current are extremely small. For this reason, it is of critical importance to discharge any static electric charge before it damages the IC.
An ESD can occur, for example, when a person touches some of the pads on the IC. This is the same static electricity that may be painfully experienced by a person who walks across a carpet on a dry day and then touches a grounded metal object. In an isolated IC, the ESD acts as a brief power supply for one or more pads, while the other pads remain floating, or grounded. Because the other pads are grounded, when the ESD acts as a power supply at a randomly selected pad, the protection circuitry acts differently than it does when the IC is operating normally. When an ESD event occurs, the protection circuitry must quickly become conductive so that the electrostatic charge is conducted to VSS or ground and is dissipated before damaging a core circuit of the IC.
While an ESD protection circuit is typically implemented to protect a core circuit from being damaged, it is still possible for the MOS transistors of an inverter within the protected core circuit to be damaged during an ESD event. The tie-off inverter, which typically includes a PMOS transistor and an NMOS transistor, is commonly implemented within the core circuit to provide a high or low signal. The gate oxide layers of the MOS transistors within the inverter can be easily damaged by a raised voltage created during an ESD event. This raised voltage may apply a severe electric stress on a gate oxide layer of the MOS transistor. For example, under the ESD conditions, there may be a large difference between the source voltage and the gate voltage of the MOS transistor, thereby creating a high source-to-gate voltage. This high source-to-gate voltage will apply severe electric stress on the gate-oxide of the MOS transistor. The gate-oxide of the MOS transistor may be damaged once it is charged to a certain voltage level. In order to reduce this stress, the voltage difference between the source and gate needs to be reduced.
Desirable in the art of inverter designs are tie-low or tie-high circuits that reduce the source-to-gate voltage of the MOS transistors within the inverter, thereby protecting the gate oxide layers of the MOS transistors from damage during an ESD event.